Description of the Related Art
According to recent trend of reducing the size of cellular or mobile phones and other communication devices, chip stack packages having higher memory capacitance within a limited chip size have been used.
FIG. 1 exemplifies a typical chip stack package. Referring to FIG. 1, it is seen that at least two layers of packages are stacked in the chip stack package and the respective packages have semiconductor chips therein. The stack chip package as in FIG. 1 has a structure that unit packages 10, 20 are electrically connected each other by means of a guide 15 attached to one side of unit packages 10,20. Solder joints(not shown) are provided between outer leads 11,21 of the unit packages 10,20 and the guide 15 for the electric connection between unit packages.
In the package as shown in FIG. 1, there are, however, drawbacks in junction reliability of the solder joints for electrically connecting the unit packages 10, 20. And, also the electric signal transmission in the chip stack package delays rather than in a chip size package. Moreover, a conventional chip stack package should include a heat sink for dissipating heat generated during operation of the package and it is impossible to stack in a chip size package shape.
As a complement to foregoing drawbacks, another chip stack packages as in FIGS. 2a and 2b are presented. Referring to FIG. 2a, a chip stack package 30 has a structure that semiconductor chips 31, 32 stacked each other are connected to a lead frame 35 by means of a tape automated bonding 33 (hereinafter "TAB"). On the other hand, referring to FIG. 2b, a chip stack package 30a has a structure that semiconductor chips 31, 32 are connected to a lead frame 35 by means of a bonding wire 37. Reference numeral 29 in FIGS. 2a and 2b is a epoxy compound.
As noted in the chip stack packages of FIGS. 2a and 2b, since a TAB or a bonding wire is used for connecting the semiconductor chips and lead frame, electric signal path is enlarged and therefore the electric characteristics of chip stack package is degraded. Furthermore, the dissipating mechanism of chip stack package is very complicated and the heat dissipation is not performed enough. The chip stack packages of FIGS. 2a and 2b are hardly applied due to those drawbacks.